In the fabrication of high-density semiconductor devices, a large number of devices, or chips, are fabricated on each silicon wafer. To maximum the number of chips on each wafer, the patterning and etching process is typically carried out over almost the entire surface of the silicon wafer. In order to maximize the number of chips that are fabricated on each silicon wafer, process equipment manufacturers have developed wafer handling equipment that minimizes the coverage of the silicon wafer during processing. Before the development of advanced wafer positioning technology, the resist used to form the lithographic patterns was removed so as to leave bare silicon at the periphery of the wafer. Thus, particulate contamination arising from contact by edge clamping devices with the periphery of the wafer could be minimized. Although the development of advanced wafer positioning equipment has led to the ability to fabricate an increased number of chips on each silicon wafer, exposure of the edge regions of the wafer can lead to the formation of particulate contamination during fabrication.
Plasma etching, for example, is a widely used technique for fabricating semi-conductor devices, such as integrated circuits, memory devices, logic devices, and the like. In a typical parallel plate plasma etching process, a silicon wafer is positioned within a vacuum chamber, between two radio-frequency (RF) powered electrodes. A reactive gas is introduced into the vacuum chamber and a plasma is ignited in the electrical field created between the electrodes. Typically, the plasma etching process is carried out to transfer a pattern from a lithographic mask into the underlying silicon substrate, or into deposit thin-film layers overlying the silicon substrate.
Shown in FIG. 1 is a schematic, cross-sectional view of a portion of a plasma etching chamber in a parallel plate plasma etching apparatus 10. A silicon wafer 12 is positioned on an electrostatic chuck 14 within the plasma etching chamber. An upper electrode 16 is positioned in parallel spaced relationship with electrostatic chuck 14. A shadow ring 18 is positioned between upper electrode 16 and electrostatic chuck 14.
With the development of wafer positioning devices, such as electrostatic chuck 14, the entire upper surface of silicon substrate 12 including a circumferential edge region 20 can be exposed to the plasma within plasma etching apparatus 10. By using an electrostatic chuck, silicon substrate 12 is securely positioned on the lower electrode within the plasma etching apparatus. Accordingly, a wafer clamp or other device that would partially cover circumferential edge region 20 of silicon substrate 12 is not necessary to position and hold the substrate on the lower electrode.
A plane view of silicon substrate 12 is shown in FIG. 2. During the plasma etching process, circumferential edge region 20 is exposed to the plasma and, depending upon the particular process ongoing within plasma etching apparatus 10, either the substrate itself or a previously deposited thin-film layer is etched by the reactive gases in the plasma. In a typical trench fabrication process used form, for example, trench capacitors or isolation structures, such as shallow trench isolation (STI) structures, a silicon etchant is used in the plasma etching process. In the absence of a clamp ring or other clamping device, the silicon etchant freely etches circumferential edge region 20. The silicon etchant is able to etch circumferential edge region 20 because this region is typically unprotected by the etching mask used to provide patterning for STI structures.
FIG. 3 is a cross-sectional view of silicon substrate 12 taken along section line 3—3 of FIG. 2. As shown in the cross-sectional view, the attack by the silicon etchant upon circumferential edge region 20 of silicon substrate 12 forms an edged silicon region known in the art as “black silicon.” The black silicon is a surface region of silicon substrate 12 in which numerous micron and submicron sized silicon filaments are formed in the substrate surface.
The formation of black silicon in a semiconductor fabrication process is problematic because the silicon filaments tend to break off during processing and can become lodged in the micron and submicron sized trenches being formed during the silicon etching process. Once a silicon fragment becomes lodged within a trench, further etching of the contaminated trench is blocked by the filament. Additionally, fragments of silicon from the filaments continue to break off during subsequent processing and can result in further contamination at later stages of device processing.
In an attempt to prevent the formation of black silicon during the plasma etching of silicon substrates, a shallow mask, such as shadow ring 18 is positioned within the plasma field as illustrated in FIG. 1. Shadow ring 18 shepards plasma field lines 24 such that the plasma field is directed away from circumferential edge region 20. While the use of a shadow ring can be beneficial in minimizing the formation of black silicon near the wafer edge, the shadow ring distorts the plasma field and can lead to non-uniform etching. Accordingly, a need existed for an improved semiconductor device fabrication process that minimizes the formation of black silicon, while avoiding plasma field distortion.